MOS 커패시터를 이용한 저면적 연속 근사화 레지스터 아날로그-디지털 변환기 구현

Abstract

Due to the development of integrated circuit technology, many of the features that have been implemented in the analog domain are easily implemented in the digital domain. Although many types of signal processing are moved to the digital domain, the need for analog signal processing in the processing of the natural signal is still important. Therefore, many systems are composed of the ADC(Analog-to-Digital Converter) and DSP(Digital Signal Processor). This thesis presents the Implementation of a low area SAR(Successive Approximation Register) ADC using MOS(Metal-Insulator-Metal) capacitor. The proposed SAR ADC consists of sample-and-hold stage, capacitor array network stage, comparator stage, SAR control logic stage, digital-to-analog converter(DAC) stage and DAC control logic stage. This SAR ADC is designed to have performance of 12-bit resolution and 1MSps(1 Mega Sampling per second). The proposed circuit is designed using Magnachip/SK Hynix 0.18μm CMOS process, and it is powered by 1.8V supply. Total chip area is reduced by replacing the MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit in this thesis showed high SNDR(Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective bit number of 11.4-bit as compared to conventional research results. The designed circuit also showed low power dissipation of 1.93mW, and small chip area of 0.51mm².