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직류 오프셋 제거기능을 가진 저전력 자동 이득 증폭기 설계

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Alternative Title
Design of Low-Power Programmable Gain Amplifier with DC-offset cancellation
Abstract
This paper presents low-power Programmable Gain Amplifier (PGA) with a DC-offset cancellation for a direct conversion receiver (DCR) to reduce chip area, cost and power. In the receiver stage, the direct conversion architecture has simplified scheme as compared to the conventional super-heterodyne architecture because IF stage could be omitted in the direct conversion architecture, and the system can be a single chip. The PGA has fully differential scheme to reduce the noises and distortions in the input signal and supply voltage. This circuit is also designed to adjust gains in the range of 4dB to 60dB in 8 steps for detecting signals with various amplitudes into the system. We designed PGA gains in 8 steps by adjusting on-resistors of 16 MOS switches and 8 resistors considering linearity and total chip size, and DC-offset circuit is based on a Miller effect technique. It is fabricated using Magnachip/SK Hynix 0.18-μm CMOS 1poly-6metal process. The proposed system showed excellent gain error of less than 0.24dB, very small die area of 0.015mm2 and low power consumption of 1.137mW.
Author(s)
김철환
Issued Date
2015
Awarded Date
2015. 2
Type
Dissertation
Publisher
부경대학교 일반대학원
URI
https://repository.pknu.ac.kr:8443/handle/2021.oak/12190
http://pknu.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001967809
Alternative Author(s)
Kim, Cheol Hwan
Affiliation
부경대학교 일반대학원
Department
대학원 정보통신공학과
Advisor
류지열
Table Of Contents
목 차

Ⅰ. 서론 01

Ⅱ. 직류 오프셋을 제거한 PGA 회로 03
2.1. PGA의 기본개념 03
2.2. 제안된 직류 오프셋 제거 PGA의 회로 구조 05

Ⅲ. 제안된 직류 오프셋 제거 PGA 회로 07
3.1. 축퇴 저항 차동증폭기 07
3.2. Gm-boosting 궤환 시스템 11
3.3. 변형된 Gm-boosting 증폭기의 이득 조절단 15
3.4. 직류 오프셋 제거 회로 20
3.4.1. 직류 오프셋 20
3.4.2. 직류 오프셋 제거 21
3.4.3. 제안하는 직류 오프셋 제거 회로 23

Ⅳ. 시뮬레이션 결과 및 분석 28
4.1. 직류 오프셋을 제거한 시간 응답 시뮬레이션 28
4.2. 주파수 응답 시뮬레이션 31
4.3. CMRR 시뮬레이션 32
4.4. 고조파 균형 시뮬레이션 34
Ⅴ. 결 론 36

참 고 문 헌 37

별 첨 39
Degree
Master
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산업대학원 > 전자정보통신공학과
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