Current Modulator를 이용하여 작은 루프필터를 가지는 위상고정루프

Abstract

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been studied. In this thesis, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V 0.18μm CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and the locking time of conventional PLL.