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Abstract

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been studied. In this thesis, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V 0.18㎛ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and the locking time of conventional PLL.