반도체 웨이퍼팹의 운영전략 시뮬레이션 분석

Abstract

In a semiconductor wafer fab(fabrication), the circuits are built up in layers on the wafers by a very large number of processes. As different layers are added to the wafer surface, the wafer lots at different production stages visit (reenter) the same processing equipment several times. Since the wafers go through hundreds of processes before leaving the fab, the fab suffers from long production flow time and high work-in-process inventories. This thesis addresses operational control problems in a wafer fab. The control problems in the wafer fab can be classified into two problems, lot release and dispatching. Lot release is a fab-level decision that determines when and how many wafer lots should be released into the wafer fab for the first process while dispatching is an equipment-level decision that determines which lot should be loaded next on an idle machine. The dispatching problems in a wafer fab can be further divided into two, sequencing for discrete processing machines and batching for batch processing machines. Most of the research works on operational control problems in the fab studied so far address the input release and dispatching problems separately. This paper examines the performance of operational control decisions including lot release, sequencing and batching, from the system's perspective. We classify the stations into bottlenecks and non-bottlenecks, and present control policies for both of them. In addition, for the batch processing machines, a control policy is presented from a system's view. A simulation model is constructed where these control policies are incorporated. Through simulation studies, the performance of the presented control policies is evaluated, and some insights on the performance of the control policies are discussed.