12-bit 1MSps SAR ADC for System-on-Chip

Abstract

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and to reuse methodologies that are collectively referred to as System-on-Chip (SoC) design. To solve these problems, analog-to-digital converter (ADC) is required in SoC. This thesis focuses on the design of successive approximation register (SAR) ADC for SoC. The proposed of SAR ADC contains Sample-and-Hold stage, capacitor array, SAR control logic stage, comparator stage, DAC stage, and DAC control logic stage. This SAR ADC is designed to have performance of 12-bit resolution. The proposed circuit is designed using Magnachip/SK Hynix 0.18μm CMOS 1Poly-6Metal process, and it is powered by 1.5V supply. To reduce chip area and power consumption, we minimized unit capacitor area and number of the total capacitors, and designed the circuit optimization as compared to conventional circuits. The proposed circuit in this thesis showed high signal-to-noise distortion ratio (SNDR) of 71.18dB, and excellent effective number of bit (ENOB) 11.53-bit as compared to conventional research results. The designed circuit also showed very low power consumption of 1.95mW, and small chip area of 0.54mm². The proposed ADC is applicable for the signal conversion of the industry system application.