Low-Power High-Linearity CMOS Radio Frequency Receiver Frontend for 24GHz Automotive Collision Avoidance Radar
- Alternative Title
- 24GHz 차량 충돌방지 저전력 고선형 CMOS 고주파 수신기 전단부
- Abstract
- Communication has experienced explosive growth world-wide in the last decade and its huge market potential is driving relentless efforts in the information industry to improve the performance of wireless communication systems. Academia has also witnessed a flourish of research activities in communications, digital signal processing and radio frequency integrated circuit design.
Fuelled by the ever increasing demand for wireless products and the advent of deep submicron CMOS, RF ICs have become fairly commonplace in the semiconductor market. This has given rise to a new breed of Systems-On-Chip (SOCs) with RF front-ends tightly integrated along with digital, analog and mixed signal circuitry. However, the reliability of the integrated RF front-end continues to be a matter of significant concern and considerable research. A major challenge to the reliability of RF ICs is the fact that their performance is also severely degraded by wide tolerances in on-chip passives and package parasitics, in addition to process related faults.
An RF front end receiver system refers to the analog down conversion stages of the wireless communication system. The Digital base-band signals cannot be transmitted directly through wireless channels due to the properties of electromagnetic waves. The baseband signals need to be converted to analog through a digital-to-analog converter (DAC), up converted to higher frequency using an up conversion mixer and then transmitted through the channel. The received signals are down converted to base band frequency and then converted to digital again using the analog to digital converter (ADC). The processes which the analog signal undergoes at the RF front end include amplification, mixing and filtering
The main wireless receiver task is to detect the desired modulated signals. Wireless receivers have to perform several functions such as tuning to the wanted signal carriers, filtering out the undesired signals, and amplifying the desired signal to compensate for power losses occurring during transmission. However, there are several receiver architectures, and the heterodyne and the direct conversion are the most popular.
In this dissertation, a modified IF receiver architecture is adopted as a compromise between the heterodyne and the direct conversion to have immunity against flicker noise, dc offset and I/Q mismatch, and to achieve higher integration. In a receiver frontend, either wired or wireless low noise amplifier (LNA) is the first gain stage after antenna. LNA should amplify all these signals without causing any significant distortion for the following stage to handle. This sets the requirement of a certain gain to the LNA. Furthermore, the sensitivity of the receiver chain is determined by sensitivity of the LNA. This requires that a little noise from LNA must be introduced to the overall receiver.
Down conversion mixers as the next stage after LNAs in receiver frontend are more vulnerable than the other stages due to their configuration. They should translate the high frequency signals to either intermediate or baseband frequency ones.
Voltage-controlled oscillator (VCO) is an independent circuit, since some self-sustaining mechanism generates a periodic stable sinusoidal signal. VCO also can be used as a part of the frequency synthesizer to produce the local oscillator signal for both down/up-conversion mixers. An ideal VCO should meet most of these specification such as low phase noise, low power, wide tuning range, high integration, small die area accuracy and low cost.
This dissertation shows that significant benefits are achieved with continued design innovations in spite to the general belief that RF circuit design is a mature subject. With the down scaling of CMOS process, efforts in CMOS RFIC design has been continuing the future for long time.
- Author(s)
- RASTEGAR, HABIBOLLAH
- Issued Date
- 2017
- Awarded Date
- 2017. 2
- Type
- Dissertation
- Keyword
- 차량 충돌방지 CMOS 고주파 수신기
- Publisher
- 부경대학교 대학원
- URI
- https://repository.pknu.ac.kr:8443/handle/2021.oak/13541
http://pknu.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002331812
- Affiliation
- 부경대학교 대학원
- Department
- 대학원 정보통신공학과
- Advisor
- 류지열
- Table Of Contents
- 1 Introduction 1
1.1 Motivation 1
1.2 Proposed Receiver Frontend Architecture 2
1.3 Objective 5
1.4 Overview 7
2 Desing of Low Noise Amplifier 11
2.1 Background 11
2.2 S-parameters 13
2.3 Power Gain 17
2.4 Stability Factor 21
2.5 Modulation Scheme 23
2.5.1 Noise Sources 25
2.5.2 Noise Figure 26
2.5.3 Output Noise of the First Stage 29
2.5.4 Sensitivity 33
2.6 Linearity 34
2.6.1 1-dB Compression Point 35
2.6.2 Third-order Input Intecept Point (IIP3) 36
2.6.3 Linearity Consideration of the Systsem Level 38
2.7 Input Impedance Matching Network 40
2.8 Design Considerations and Analysis 41
2.8.1 LNA Descriptioin 41
2.8.2 LNA Design 44
2.8.2.1 Fundamental 44
2.8.2.2 Nonlinear Base Capacitance in Bipolar Transistor 47
2.8.2.3 Phase Adjustment by Feedback Capacitance 49
2.8.3 Design Consideratioins 50
2.8.4 Implementation 51
2.8.5 Measurement set-up 54
2.8.6 Experimental Validation 56
2.9 Measurement Results 57
2.9.1 S-parameters and Noise Figure Measurement 57
2.9.2 IIP3 and Satbility Factor 60
2.10 Summary 64
3 Design of Low Power and Low Voltage Mixer 65
3.1 Background 65
3.2 High Linearity Techniques 68
3.3 Mixer Fundamentals 70
3.4 Main Characteristics of Mixers 72
3.4.1 Conversoin Gain 72
3.4.2 Local Oscillator Power 73
3.4.3 Noise Figure 74
3.4.4 Port to Port Isolation 76
3.5 Active Mixer Architecture 72
3.5.1 Unbalanced Mixer 77
3.5.2 Single-balanced Mixer 79
3.5.3 Double-Balanced Mixer 81
3.6 Design Consideratonis and Analysis 83
3.6.1 Mixer Description 83
3.6.2 Mixer Analysis 84
3.6.3 Results and Disscussions 88
3.7 Summary 93
4 Design of Voltage-Controlled Oscillator 94
4.1 Background 94
4.2 Start-up Considerations 97
4.3 Steady-state Considerations 101
4.4 Phase Noise in LC Oscillators 103
4.4.1 Linear Time-Invariant Phase Noise Analysis 103
4.4.2 Linear Periodically Time-Varying (LPVT) Phase Noise Analysis 106
4.5 LC VCO Topologies 108
4.5.1 Single Cross-Coupled LC VCO Topology 109
4.5.2 Complementary Cross-Coupled LC VCO Topology 111
4.6 Design Trade-offs 113
4.7 VCO Description 116
4.8 Proposed Current-reuse LC VCO 119
4.8.1 Start-up Considerations 120
4.8.2 Analysis of Output Voltage Swings 124
4.8.3 Frequency-Dependent Negative Resistance 128
4.8.4 Phase Noise Analysis 131
4.9 Results and Discussions 133
4.10 Summary 139
5 An Integarated High Linearity CMOS Receiver Frontend for 24-GHz Applicatoins 140
5.1 Background 140
5.2 Proposed Receiver Frontend Architecture 141
5.3 Design and Analysis of CMOS Circuit Blocks 144
5.3.1 LNA 144
5.3.2 Mixer 151
5.3.3 Frequency Divider 156
5.3.4 Balun 158
5.4 Results and Discussions 162
5.5 Summary 170
6 Conclusion 171
6.1 Conclusions 171
6.2 Future Works 175
References 177
List of Publications 191
- Degree
- Doctor
-
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