강판 결함 검출용 시스템-온-칩 설계

Abstract

Abstract In this thesis, we research on the design and fabrication of the SoC(System-on-Chip) for detecting steel plates defects. Core circuits in such a System-on-Chip are composed of PGA(Programmable Gain Amplifier) and SAR-ADC(Successive Approximation Register-Analog to Digital Converter). In general, systems for detecting steel plates defects are fabricated by PCB, but it has several problems in terms of production cost, power consumption and area which occupy in a system. However, in case of being implemented by not PCB but SoC, it has the advantages of low cost, low power consumption and small area. Therefore, to solve problems of system fabricated by PCB, we implement core circuits in a system for detecting steel plates defects into SoC. In this thesis, the PGA, the first core circuit in a SoC for detecting steel plates defects, was designed by using a fully differential amplifier to minimize external noise, and by using degeneration resistance and CMOS switch-on-resistance to implement low power and small area. The PGA was also implemented by using layout optimization techniques of common matching and latch to minimize area which occupies in a SoC. As a result, we identified that the PGA for a SoC has seven gain control functions and very low gain error of less than 0.18dB. It also showed very low power consumption of 0.47mW in a supply voltage of 1.8V and small area of . The SAR-ADC, the second core circuit in the proposed SoC, consisted of sample-and-hold stage, capacitor array network stage, SAR control logic stage, comparator stage, DAC stage and DAC control logic stage. This SAR-ADC was designed and implemented to minimize area and power consumption in a SoC, and to have performance of 12-bit resolution and 1MSps(Mega Sampling per second). As a result, the SAR-ADC showed excellent SNDR(Signal to Noise Distortion Ratio) of 69.53dB and ENOB(Effective Number of Bit) of 11.26-bit. It also showed low power consumption of 3.6mW in a supply voltage of 1.8V and small area of The proposed SoC in this thesis was designed and fabricated by using 0.18 1Poly 6Metal CMOS process from Magnachip semiconductor, Co., Ltd. The proposed SoC showed very low power consumption of 4.07mW and very small area of .