24GHz Frequency Synthesizer for Automotive Radar Applications

Abstract

In the recent years the needs for high integration and low cost wireless transceiver modules have been raised and the power consumption is a great consternationfor radio frequency integrated circuit (RFIC) engineers. Rigorous attempts havebeen made to provide RF systems in the GHz range using the low-cost and low-power CMOS technology. Frequency synthesizer (FS) is important part of the automotive radar system.Low phase noise and high spectrum purity arevital for its good performance. Frequency synthesizer performs down-conversion and up-conversion operations in automotive radar system. Frequency synthesizer is a critical block of an automotive radarsystem, and it has large power consumption since it operates at a high frequency in the automotive radar transceiver. The voltage-controlled oscillator (VCO) and the high frequency divider are the two most important building blocks of frequency synthesizer. Power consumption and channel selection of frequency synthesizer are limited by these two critical blocks. In this thesis, we have carried a detailed analysis on the 24GHz frequency synthesizer. Thecircuit is designed using 65nm RF CMOS technology. TheVCO is designed incurrent-reuse technique along with the NMOS cross-coupled transistors to enhance the negative resistance requirement of oscillator. Thecurrent-reuse transistors are biased in sub-threshold region to save power consumption. To improve the phase noise performance in the designed VCO the N/PMOS cross-coupled transistors operate in differential mode providing a virtual ground. This virtual ground is connected with source of NMOS cross-coupled transistors through inductor todecrease the phase noise.The inductor source tuning technique isalso implemented in place of tail current shaping transistors used in conventional VCO to decrease the phase noise.To decrease the power consumption in the proposed circuit the frequency divider is implemented with master-slave frequency divider and true-single-phase-clock(TSPC) frequency divider scheme. In the designed circuit, the reference frequency is 100MHz, and the output frequency is24GHz-25.8GHz. The proposed frequency synthesizer showed low power consumption of 3.52mW with the supply voltage of 0.9V. The VCO also showed a low phase noise of -117dBc at a frequency of 1MHz and -138.50dBc at 10MHz. The proposed frequency synthesizer showed a low phase noise of -116.3dBc at 1MHz and-134.7dBc at 10MHz.