Design of a 24-GHz Phase-Locked Loop for Automotive Radar Applications

Abstract

The essence of our present technology back-up has been a design of a high-frequency wireless communication system. Larger GHz-frequency spectrum in wireless systems has recently attracted much attention from the researcher. One of the critical components in the wireless communication system at the receiver front-end is the phase-locked loop (PLL). In this thesis, we have carried out an in-depth analysis and design of 24-GHz PLL. The circuit is designed using 65-nm RF CMOS technology. It is designed using current-reuse technology along with the NMOS cross-coupled transistors that are considered for VCO to enhance the negative resistance requirement of the oscillator circuit. For better roll off without a ripple in the pass-band, we designed a third-order Legendre filter. It yields a good transient response and also results in flat frequency response. The designed circuit is characterized by the maximum number of possible roll off and is found consistent with the monotonic magniture response in the pass-band.