아날로그 대역 선택 루프를 이용한 위상 고정 루프

Abstract

In this thesis, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V 0.18μm CMOS process and proved by HSPICE simulation.