Development of a Highly Efficient 24GHz CMOS RF Transmitter Front-End for Automotive Radar Application

Abstract

Automotive radar technology has advanced dramatically over the years. This technology is becoming more popular as a key concept in collision avoidance and concern for automobile safety systems. The fundamental aspects of collision avoidance include detection, prediction, and hazard analysis. Automotive radar is an important sensing technique for advanced driver assistance systems (ADAS) and self-driving cars. Next-generation automotive radar technology will be more cost-effective and size- conscious relying on CMOS-integrated radar system-on-chips (Radar-SoC). CMOS technology has been the most appealing implementation of low-complexity and low-cost chip design. Following the Federal Communications Commission (FCC), the previous decade’s investigations were mostly focused on advancements in unlicensed bands at 17GHz, 35GHz, 49GHz, 60GHz and 77GHz for automotive radar applications. Currently, the major focus is to develop low-power highly integrated transceivers at these high frequencies. Thus, a significant research effort is now being undertaken. The ADAS comprises long range radar (LRR) up to 150 meters and short range radar (SRR) up to 30 meters. The prior research implies that during the past 15 years, 24GHz SRR has been studied by industry and academia. Therefore, next-generation radar sensors may be needed to support the 24GHz band for compatibility and reduced overall cost. In this thesis, a CMOS transmitter front-end with a detailed analysis of integrated circuits suitable for 24GHz SRR applications is described. The power amplifier (PA) is the most power-hungry component in a transmitter-receiver chain. The PA is designed for to achieve maximum power efficiency. However, it is challenge to achieve good efficiency within the required range in automotive radar. In particular, it becomes hard in the case of integrated CMOS PAs. Therefore, this thesis provides a detailed analysis of dual-mode stagger-tuned power amplifiers and offers a design to match the radar standard. The thesis also highlights the optimization of PA using an adaptive genetic algorithm (AGA) and provides a theoretical analysis of stagger-tuned power amplifiers by deriving an expression for the total efficiency of the PA. Besides, to drive a PA and to match a 50 Ω load, a CMOS up-conversion mixer is required. Also, the mixer must be configured in such a manner that it can handle the available maximum power at the power amplifier's input. Unless power consumption is very high, the low output impedance of the up-conversion mixer results in poor conversion gain (CG) and in certain cases conversion loss, too. Hence, to achieve the desired output power at low CG, large amplitude signals are often delivered at the input of the up-conversion mixer necessitating good linearity. Therefore, to emphasize on the significant point, this thesis also configures an up-conversion mixer for 24GHz radar application. The designed mixer contains dual transconductance path (DTP) combined with improved cross-quad trans-conductor (ICQT) to enhance the mixer linearity. The DTP's main transconductance path (MTP) incorporates a common source (CS) amplifier, while the DTP's secondary transconductance path (STP) is constructed as an ICQT. Two inductors with bypass capacitors are connected at the common nodes of the mixer's transconductance and switching stages. These two inductors serve as a resonator to improve the power gain and isolation of the mixer. The PA and mixer design are implemented by 65nm CMOS technology. The designed dual-mode PA showed S21 (power gain) of 28.4±0.5 dB in synchronous operation and 22.1±0.5 dB in staggered operation, respectively. The proposed PA also showed excellent Psat of 14.21dBm, high PAE of 47.5%, and high-linearity IIP3 of PA of 14.5 dBm. The proposed mixer showed IP1dB of 0.9 dBm, OP1dB is 3.9 dBm, and conversion gain of 2.49dB at the operation frequency of 24 GHz.