Development of a Highly Linear RF Transmitter Front-End for 24GHz Automotive Radar Application

Abstract

One of the emerging technologies in the today’s modern world is automotive radar technology. There has been a significant increase in the radar industry as a result of the goal to provide safe driving and comfort amenities in future automobile vehicles. In modern vehicles, radar technology is used to enable and implement intelligent and autonomous features. A number of high-end vehicles have recently been equipped with automotive radar to provide vital safety and comfort features for the driver. Adaptive cruise control and autonomous emergency braking systems are some of the technologies that are parts of them. In an emergency situation, a vehicle's autonomous emergency braking system allows it to descend sharply without any driver assistance to mitigate the risk of a collision. However, the implementation of these features has been limited to highly regarded cars due to the high cost of sensing technology, which has so far confined them to high-end motor vehicles. It is essential that radar systems become more affordable if they are to be a part of all vehicles in the future. Conventional CMOS technology was originally developed for this purpose, and this is the key reason for its use today. With the rapid adoption of CMOS technology in the area of radio frequency (RF) integrated circuits, access to low-cost high-performance solutions has been made possible, and the technology has quickly taken over the market. Today's complicated mixed-signal systems are designed using CMOS technology, which has emerged as a viable option for integrating these systems. Despite this, a considerable part of energy is still lost as heat because of the amplifier's efficiency and linearity constraints, resulting in severe performance deterioration and reliability issues. To achieve high linear transmitter designs for CMOS front-end in automobile radar applications, it is evident that high linear transmitter designs are critical. In recent years, after the Federal Communications Commission in granted unlicensed bands for several wireless applications, a very intense research effort has been underway to develop highly integrated CMOS solutions that operate in the K-Ka band of millimetre wave frequencies (mm-waves). As a result of the granting of these unlicensed bands, usually direct conversion undertaken at RF frequencies, is able to achieve high levels of integration and to eliminate the need for image reject filters as well as IF filters in conventional direct conversion. Despite this, the development of quadrature local oscillators (LOs) for the Ka bands is still difficult due to the low-quality factors of the variable capacitors that are used as tuning elements in voltage-controlled oscillators (VCOs), their limited tuning components, and the power consumption of the PLL dividers. One of the most power-demanding components of a TX system is the power amplifier (PA). As a result, getting good linearity within the radar range required by automobiles becomes a challenging task, particularly when it comes to integrated CMOS PAs. Hence, high linear circuit approaches are presented in this thesis, along with a CMOS TX front-end for an automotive radar at 24 GHz. The CMOS up-conversion mixers are often called upon to drive an external power amplifier that has a 50 W load. The mixers need to be designed to take care of the maximum power that is required at the PA's input. A low output impedance of an up-conversion mixer often results in a low conversion gain (CG), and often a conversion loss, unless the mixer consumes a large amount of power which would otherwise result in a very low conversion gain. Whenever a low CG condition exists, it is necessary to apply large amplitude signals at the input of the mixer to achieve the output power required, thus requiring high linearity at the input of the mixer. Up-conversion mixers based on CMOS technology with a frequency range of 24 GHz have been reported, but their linearity is still required to be improved. Further, this thesis proposes a design procedure and highlights the design process in 65 nm CMOS technology as well. This thesis proposes a modified current reuse configuration for a minimum-power and low-phase noise VCO. With its minor consumption of power, only 1.35 mW at 0.9 V input voltage, the proposed current reuse VCO showed an extremely low phase noise of -117 dBc/Hz. It has also showed a wide tuning range of 26.4 %. The power output of the VCO at the frequency of 24.5 GHz showed -7.9 dBm. As parts of the thesis, two novel mixer architectures are implemented, and first mixer design includes an improved derivative superposition (I-DS) technique with tuneable capacitive cross-coupled common source (TCC-CS) transistors that is applied to the mixer’s transconductance stage to achieve a high linearity. The second mixer design with the tranconductance stage consists of a common source (CS) route with neutralization technique and dual capacitive cross coupled-common gate (DCCC-CG) route, and n/pMOS cross-coupled switches in the switching stage to achieve the high gain and high linearity concurrently. A novel PA also described in this thesis which operates at 24 GHz. The power gain of the proposed PA is 28.4 ± 0.5 dB and Psat of PA is 14.21 dBm. The group delay (GD) variation of PA is 57 ± 10 ps at 24 GHz. A proposed PA exhibits good linearity (IIP3) of 14.5 dBm due to the implementation of resistive feedback technique and achieves a PAE of 47.5% at 24 GHz. The chip area of the designed PA is 0.406 mm2. High linearity, high gain, and bandwidth results of the proposed PA make it a good choice for the development of future 5G wireless networks.