Development of High Efficient 24 GHz CMOS Radio Frequency Receiver Frontend for Automotive Collision Avoidance Radar

Abstract

In the future, the wireless communication devices for radar and satellites will need to support numerous standards and should be constructed in the form of a system-on-chip (SoC). This will allow for significant reductions in cost, area, pin count, and power consumption, among other factors. On the other hand, the design of a completely on-chip CMOS wideband receiver front-end that is capable of concurrently processing multiple radar and satellite signals becomes a multifold complicated task when applied to such a device. In addition, the high-power out-of-band (OB) blockers that are naturally present in radio spectrum may cause the receiver to become increasingly non-linear and may even cause it to become saturated at times. Consequently, it is necessary to implement the appropriate procedures for the rejection of blockers. Communication has experienced explosive growth world-wide in the last decade and its huge market potential is driving relentless efforts in the information industry to improve the performance of wireless communication systems. Academia has also witnessed a flourish of research activities in communications, digital signal processing and radio frequency integrated circuit design. The creation of a CMOS high-performance low-noise wideband receiver architecture that also includes a subthreshold out of band sensing receiver will be the major emphasis of the work that will be done in this line of study. In addition, many different reconfigurable mixer topologies have been developed for the purpose of improving the performance flexibility of wideband receivers for incoming standards. Analyzing the expected modulated signals is the primary responsibility of a wireless receiver. To recover the original signal strength after transmission losses, wireless receivers must execute many tasks, including tuning to the required signal carriers, filtering out the unwanted signals, and amplification. Nonetheless, there are a number of receiver topologies, the most common of which being heterodyne and direct conversion. A heterodyne receiver typically converts the incoming radio frequency signal into one or more intermediate frequencies before modulation. To prevent the folding of errant signals, picture rejection and IF filters play a crucial role in this layout. The heterodyne design is unsuitable for monolithic integration due to the existence of several cumbersome and costly RF/IF filters. Alternate heterodyne design has been presented as a solution to the growing cost and footprint of the RF frontend. In the initial frequency downconversion, for instance, direct conversion transforms the RF signals into the IF-zero baseband. Since off-chip IF filters aren't required, the receiver frontend may be built in a cheap and efficient design. Despite the direct conversion architecture's higher performances, its dc offset and LO leakage make it difficult to design and execute individual blocks, which in turn makes it necessary to loosen the requirements of the system as a whole. The low noise amplifier (LNA) is the first gain stage (after the antenna) in a wired or wireless receiver frontend. Several requirements must be met simultaneously, making the design very difficult. In CMOS technology for RF CMOS integrated circuits, the design and implementation of single-chip transceivers has previously been shown (ICs). The main wireless receiver task is to detect the desired modulated signals. Wireless receivers have to perform several functions such as tuning to the wanted signal carriers, filtering out the undesired signals, and amplifying the desired signal to compensate for power losses occurring during transmission. However, there are several receiver architectures, and the heterodyne and the direct conversion are the most popular. Typically, a heterodyne receiver translates the desired input RF signal onto one or more preselected intermediate frequencies before modulation. In this architecture, image rejection and IF filters are vital to avoid folding of interfering signals. Because of presence of several bulky and expensive RF/IF filters, the heterodyne architecture is not suitable for monolithic integration. Enforced by the trends to the cost and size of the RF frontend, alternative heterodyne architecture has been proposed. For instance, direct conversion technique converts the RF signals to the IF-zero baseband in the first frequency downconversion. Therefore, the receiver frontend can be realized in low cost and low power architecture due to the unnecessary off-chip IF filters. Despite superior performances of direct conversion architecture, it suffers from the dc offset and LO leakage which leads to complicate the design and implement of individual blocks to relax the specifications of system. The design and implementation of single-chip transceivers have already been demonstrated in CMOS technologies for RF CMOS integrated circuits (ICs). For wireless communication circuits, voltage-controlled oscillators (VCOs) are one of the transceivers key elements. Oscillator is an independent circuit, since some self-sustaining mechanism generates a periodic stable sinusoidal signal. VCO also can be used as a part of the frequency synthesizer to produce the local oscillator signal for both downconversion and upconversion mixers. Oscillation can be sustained by providing the system with an appropriate amount of positive feedback or negative resistance that can compensate any loss in the circuit. Due to the better relative phase noise performance of inductance-capacitance (LC) tank, oscillators are preferred to ring oscillators for monolithic integration in CMOS technology. Beside the limitations in the applied semiconductor technology an ideal VCO should meet most of these specification such as low phase noise, low power, wide tuning range, high integration, small die area accuracy and low cost. This dissertation shows that significant benefits are achieved with continued design innovations in spite to the general belief that RF circuit design is a mature subject. With the down scaling of CMOS process, efforts in CMOS RFIC design has been continuing the future for long time for use in vehicular automotive radar systems.