주파수-전압 변환기로 잡음이 개선된 이산시간 루프필터 위상고정루프

Abstract

In this thesis, a Discrete-time Loop Filter(DLF) phase-locked loop with a Frequency-Voltage Converter(FVC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the FVC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FVC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with HSpice using the 1.8V 180nm CMOS process.