저전력 12비트 SAR 아날로그 디지털 변환기 설계

Abstract

In the near decade, countless signals and information are being exchanged for the growing demands of 5G in our daily lives. There is also phenomenal development in integrated circuits, and those are used for this massive amount of information in various types of devices. Our speech is an analog signal, but digital signals are found in electronic components. However, digital signals cannot be directly interpreted by humans, so a data converter is required. This paper presents a 12-bit successive approximation register(SAR) analog-to-digital converter(ADC). The proposed SAR ADC consists of a sample-and-hold stage, a network capacitor array stage, a SAR control logic stage, a comparator stage, a DAC control logic stage and a DAC stage. In an addition, the ADC is also being used to convert the processed digital signal back into an analog signal, and it is equipped with capacitors, resistors, and computational amplifiers to retrieve the original signal. The proposed circuit is designed by using the 1poly-6metal 0.13µm CMOS process, and it operates at a supply voltage of 1.2V. In contrast with traditional performance, the designed ADC showed a very low power consumption of 60.07µW and the smallest die area of 0.???mm2 as compared to conventional results. This circuit also exhibits an outstanding effective number of bits(ENOB) of 12.02bits and high signal-to-noise distortion ratio(SNDR) of 74.17dB. Furthermore, the sample-and-hold stage which is placed at the front end of the SAR ADC is developed to reduce the body effect, and one input clock is intended to minimize unnecessary power consumption and operation.