Fractional ripple 보상 PFD를 이용한 fractional-N 주파수 합성기 설계

Abstract

In this paper, We propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). We used a new PFD architecture with two different edge detection method. We suppressed the influence of fractional ripple by limiting a maximum width of the output signals of PFD, therefore the fractional ripple compensation can be done. The proposed PLL was simulated by HSPICE using 0.35m CMOS parameters. The simulation result shows that this type of PLL is able to fast lock, and reduce phase noise and fractional spurs. The behavioral simulation of the proposed fractional-N PLL with a ΔΣ modulator was carried out by using MatLab to determine if the architecture could achieve the objectives.