FPGA Implementation of Programmable Digital FIR/IIR Filter

Abstract

Recent years, computer vision and image processing applications acquired more attention than ever before. Edge detection is a preprocessing level application which can be further used for object detection and tracking applications. However, these high-volume applications require a lot of hardware resources and computation time. In this research, we proposed an area-efficient and a high-speed system-on-chip (SoC) system to perform the image filtering application. We proposed a combination algorithm of median and Sobel filter to filter out the noise present in digital images and find out the edges. The design uses multiplier-less architecture which results in an area-efficient system. To implement edge detection of a noisy RGB color image, the HiTechLogic’s AFPE-003 SoC platform is used. The proposed algorithm is successfully implemented and the resultant Sobel edge detected image is displayed on the liquid crystal display (LCD) display. The system achieved a run time of 0.16s and utilized 16% of logic elements.